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Experience
● Developed a C++ based tool to automate the process of bitstream generation for multiple FPGA’s after synthesizing the functions.
of a C based design using Xilinx High-Level-Synthesis(HLS) tool and Xilinx Vivado Design Suite and also to generate an
executable file from the C design to verify the functionality of the bitstream on an FPGA via UART interface.
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Developed various TCL scripts for generation of bitstreams and ip’s for PQC algorithms and implemented it on an
Artix-7 FPGA and also generated power,area and timing reports with medium confidence for further analysis.
● Generation of netlist for the ASIC implementation of the PQC algorithms using a 28/32nm library from Synopsys DC.
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Projects
FPGA Emulation of 32-bit MIPS Processor Performing RC5 Algorithm(VHDL, Vivado Design Suite)
●Designed a single cycle 32-bit single cycle microprocessor using VHDL on Xilinx Vivado and emulated it on an Artix-7 FPGA via
UART interface for data input and completed the RTL implementation.Developed assembly codes for RC5 to test the processor.
● Performed synthesis, simulation-based verification using RC5 algorithm to verify MIPS processor using assertion based test
benches and VHDL text IO to validate the test cases. Used Vivado HLS tool to optimize the RC5 algorithm.
FPGA Based Hardware Crypto Module Hacking(Verilog, C++)
●Developed wrapper files consisting of seven segment display modules, UART interface etc. in Verilog for the AES encryption
codes, generated from a C-based AES design using Xilinx HLS tool and generated the bitstream and implemented it on an FPGA
● Created a C++ code to hack the UART interface and obtain the intermediate results after round one of the AES encryption from
the FPGA(Artix-7) and perform a scan attack by analyzing the intermediate results to obtain the AES secret key.
ASIC Implementation of 256*4b SRAM-BIST(Built-In-Self-Test)(Verilog, Modelsim, Synopsys Design Compiler, PrimeTime)
● Designed a hardware module BIST(Built-In-Self-Test) that used Blanket, Checkerboard and March for testing the functionality of
a 256*4b SRAM using the Synopsys Design tools.
● Synthesized and generated the netlist from the Verilog code on a 28/32nm library using Design Compiler, checked for the timing
violation in PrimeTime and finally used the IC Compiler to place and route the optimized BIST design.
64-bit SRAM Design Using 45nm Technology(Cadence Virtuoso:Schematics & Layout)
● Designed address registers, PRE-charge circuit, row decoders, sense amplifier, read and write circuitry with a read margin of 20%
and write margin of 30% for a 64-bit SRAM with a power supply of 750mV on Cadence Virtuoso using 45nm technology.
● Optimized the area and timing delays by static and dynamic logic design styles to achieve a 2.1GHz operating frequency with an
area of 0.79μ sqm. and also created physical layout for the SRAM cell array and checked for clean DRC and LVS.
5-Stage MIPS Simulator Implementation Using C++
● Emulated a 32-bit 5-stage(Fetch,Decode,Execute,Memory) pipelined MIPS processor with a set of MIPS instructions in C++.
● Incorporated MIPS functionalities like RAW hazard, stalling, forwarding and branch prediction and interfaced register file,
ALU, instruction and data memory according to MIPS ISA.