Hi, I'm Amey Somwanshi. I'm an Electrical Engineering graduate (M.S) from IIT, Chicago. From my childhood, I have remained fascinated with electrical engineering. I decided to make my fascination a reality by choosing it as a career and pursued a bachelor's in Electronics.
During bachelors, I received many opportunities to work on knowledge-driven projects and internship. After completing my bachelors, I received an offer from Capgemini to initially join as a DBA and they promised me a hardware engineering role later. But due to reasons, they couldn't honor their promise and I was stuck doing DBA work. So, I quit the job and came here to pursue my dream. In my time at school, I did many innovative projects and some research to get a more wholesome picture of what being an MS-EE major had to offer. I am ready, more than ever to move on to a more professional setting in my area of expertise to solve the challenges plaguing our industry.
I'm hardworking, passionate, knowledge-driven, and continuously seek learning opportunities. My hobbies are playing instruments (keyboard), traveling, and reading. If given a chance, I would like to prove I'm a worthy candidate for any desired role.
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Experience
• Research Assistant, DA lab, Illinois Institute of Technology, Chicago, USA July 19’ – Dec 19’
• Worked on simultaneous clock gating and power gating to reduce leakage power and delay.
• These parameters were further optimized using various tools like HSPICE.
• Student Assistant, Keating Sports Center, Illinois Institute of Technology, Chicago, IL, USA July 19’ – Dec 19’
• Help with day to day activity and functioning of the Keating sports center at IIT.
• Organize and ref various sports like badminton, volleyball, cricket.
• Database Administrator, Capgemini, Mumbai, India Oct 15’ – Dec 17’
• Capacity planning, database design, performance monitoring, and troubleshooting.
• Maintained the authorization of details, data backup and its recovery (SQL, Linux)
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Projects
• Design and Synthesis of Central Processing Unit (CAD Flow) Mar 18’ – May 18’
• Implemented 32-bit registers using module repetition and muxing when needed on Verilog.
• Enhanced performance of ALU by changing the implemented adder architecture to a CLA adder.
• Implemented RTL to GDSII using Cadence Encounter. Performed on Virtuoso using ASIC design flow.
• Simulation of CPU, Cache, Bus and Memory Datapath (VHDL) Mar 18’ – May 18’
• Implemented operation of a 32-bit version of the MIPS processor using the VHDL in Modelsim from the scratch.
• CAD tools design for STA by using Tcl/Tk and C programming (CAD) Mar 18’ – May 18’
• Developed graphic interface for STA graph and take user’s ip using TCL/TK.
• Developed C program to do arrival required and slack time analysis.
• C program was invoked from Tcl/Tk and the final output was printed on GUI.
• Implementation of power and clock gating techniques in the circuit (Power) April 19’ – May 19’
• Implemented MTCMOS power gating with the help of MONTE CARLO simulation at circuit level design using HSPICE.
• Worked on manual TCG insertion on netlist.
• Worked on the enhancement of PG by using stepwise wake-up and two pass switching control techniques.
• Implementation and analysis of low power FinFET Circuits (Power) Mar 19’ – May 19’
• Designed LP, SG and IG modes of inverter and SRAM cell with FinFET device.
• Compared its delay with power using HSPICE.
• Impact of PG, OI. Comparison study of leakage on Ripple carry adder (Power gating) April 19’ – May 19’
• Designed entire circuitry on Virtuoso schematic editor. Measurements made on HSPICE.
• Power gating schemes like MTCMOS, SCCMOS, ZZSCCMOS in FinFET configs experimented with.
• HDL implementation of Dynamic Branch Predictors on ModelSim (COMP ARCH) April 19’ – June 19’
• Predictors were made using small generic blocks (counters, shift registers, and mux) in VHDL on Modelsim.
• Tried both local (1b, 2b) and global predictor ((4,2) correlation predictor using global branch history).
• Battery Management System for Hyperloop Pod Design competition at SpaceX HQ, CA Oct 18’ – Dec 19’
• Power-train design on Simulink using combinations of small battery cells in blocks and configurations.
• DPT Inductive Switching simulation on diode for analysis of reverse recovery effects on LTSpice. Oct 18’ – Dec 18’
• Observe switching transients without heating devices. Particularly used in BJT's and FET's