I am a Recent Graduate from Arizona State University with a Masters Degree in Electrical Engineering with specialization in Electronics Mixed Signal Circuit Design.
I am seeking Full time opportunities in Digital IC Hardware Design.
I have research experience in Radiation Hardening and modelling soft errors in SoC. The objective of the research project was to create a test-chip (RTL-to-GDS) which can measure the length of a pulse generated by a single effect transient (SET) in combinational structures and single event upset (SEU) in sequential/memory blocks.
I have 1.5 years of experience working in the Electrical Engineering department at ASU as a Teaching Assistant where I assisted graduate students on Coursework on:
EEE498: Constructionist approach to Microprocessor design:
Assisted students in projects related to RTL Designs, DC Synthesis and Verification using System Verilog.
EEE425/591: Digital Systems and Circuit: Assisted students on projects related to Digital IC design and simulation using HSPICE, Physical Layout Design in 32nm PDK and performing DRC and LVS checks.
My projects on RTL Design and Verification using System Verilog includes:
Design and implementation of Microcode Engine and RISC-V processor.
Other design includes: Sequential Multiplier, Divider, FIFO, LIFO, Square-Root, Fair Arbiter, FIR filter, sort-6 and Booth Multiplier.
I have successfully verified all the above design blocks using System Verilog Assertions.
My top Skills are:
Python-3, System Verilog Assertions, Functional Coverage, UNIX shell scripting, Perl System Verilog for Design,Simulation, Timing, Analysis, and Synthesis.
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Experience
1. Graduate Research Aid: GEN-LAB, Arizona State University (Sept 2018- April 2019)
The objective of the project was to create a test-chip (RTL-to-GDS) which can measure the length of a pulse generated by a single effect transient (SET) in combinational structures and single event upset (SEU) in sequential/memory blocks.
Designed a Process Portable Radiation Effect test-structure consists of NAND and NOR chains using 14nm GF cells.
Modeled a double exponential current source to inject the pulse at the first stage of the circuit which successfully created soft errors in the consecutive stages of the chain structure.
Designed a top-level RTL model to simulate low to high and high to low transitions at different structural hierarchies.
Used a scan chain structure to detect the point of injection and the resultant transition at different hierarchical blocks.
2. Graduate Teaching Assistant: Department of Electrical Engineering, ASU(Jan 2019–May 2020)
Teaching Assistant for the course Constructionist approach to Microprocessor design:
Assisted students in projects related to RTL Designs, DC Synthesis and Verification using System Verilog.
Teaching Assistant for the course Digital Systems and Circuit: Assisted students on projects related to Digital IC design and simulation using HSPICE, Physical Layout Design in 32nm PDK and performing DRC and LVS checks.
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Projects
1. Design and Verification of a Microcode Engine (System Verilog, Genesis2)- Nov 2018
Designed a Microcode-engine to perform instructions such as ADD, SUB, MUL, LOOP, NOOP, BEQ, BNEQ by having an interface with the scratch memory. Verified the correctness using test vectors for all the operations.
Performed synthesis and achieved timing convergence under 300ps clock period.
Successfully optimized the design to meet area and power requirements of 4800um2 and 293uW.
2.Implemented a 5-stage pipelined RISC-V processor (System Verilog, Genesis2)- Nov 2019
Designed a RISCV processor to perform assembly instructions by having an interface with ICACHE and DCACHE.
Wrote testbench for the Caches, Decoder, Hazard unit, Pipe-Register unit, sequential Multiplier and Divider blocks.
Implemented pipeline and achieved IPC of 0.25 at 300ps clock period.
3.RTL Design and Verification (System Verilog, System Verilog Assertions, VCS) Aug 2018-Dec 2018
Hardware implementation of FIFO, LIFO, Square-Root, Fair Arbiter, FIR filter, sort-6 and Booth Multiplier in Genesis2.
Increased the throughput by pipelining the design and performing power, area and timing optimizations.
Implemented System Verilog Assertions in testbenches to validate the functionality of the designs.
4.RTL to GDSII of a Convolution & Average-Pooling Engine (Cadence Innovus, ASAP7 PDK)- March 2018
Designed an RTL which performs convolution and average pooling on image pixels using 3x3 image kernels.
Optimized the design to meet the minimum area and implemented pipelining to maximize throughput.
Synthesized the design using DC synthesis and performed Automatic Placement and Route using Cadence Innovus.
5.Physical layout design of a 4X16 Decoder with a 16×16 RF array (Cadence Virtuoso, 7nm PDK) - Feb 2018
Designed a 4-to-16 decoder and a 16X16 Register File using Cadence Virtuoso in 7nm FINFET PDK.
Minimized the worst-case delay by sizing the critical path using Logical Effort under a given quality matrix.
Simulated and verified the design functionality under SS, SF, FS and FF corner using an HSPICE testbench.
6.Designed a Data Analysis program for a FMCW RADAR (Python, PyCharm)-Aug 2018
Developed a python code which reads in data and calculates the velocity and range of the moving targets.
Streamlined the program to calculate the sweep indices, perform matrix conversion in a 2D array under a frequency domain, eliminates spherical spreading, performs windowing, padding and FFT on the data set.
Plotted amplitude vs range and time vs range to derive the noise floor and the heat map.