What’s next for memory and storage?

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This blog briefs about the following: 1. Scaling Trends 2. Cons of traditional memories 3. Next generation memory device technology 4. Future memory device technology In today’s dynamic world, speed and storage are the key factors of most innovations. Hence, its crucial that one is updated with the latest trends that break barriers of conventional memory technologies. Be prepared to wave goodbye to traditional memory tech and be astounded by future advancements in the world of data storage.


For memory devices to become increasingly dense, feature sizes must shrink. Both gate oxides and gate lengths need lower voltage to avoid an increase in electrical field.

Unfortunately, it is more difficult to yield high-speed devices for low voltage ICs than it is for high voltage parts

The development of high-density EPROMs has slowed due to the evolution of flash memories. However, like other technologies, low-voltage parts are available. The low-voltage supply is only used for read operations. High voltages are required for the write operations.

DRAM cell scaling down to a 17nm design rule has already been productized by major DRAM players including Samsung, Micron and SK Hynix . Currently, they are developing 16nm and 15nm or beyond, which means the DRAM cell design rule might be able to further scale down to sub-15 nm without adopting Extreme Ultraviolet (EUV) lithography for DRAM cell patterning.

The cell design scaling down process is slowing due to many scaling issues including patterning, leakage and sensing margin.

Bit density on DRAM die reached 0.237 Gb/mm2 on Samsung’s 1y nm LPDDR4X 8 Gb die, which is a 25.4% increase from the 1x LPDDR4X die. Micron recently introduced its 1y nm 8 Gb DDR4 DRAM die with 0.205 Gb/mm2, a 22.7% increase from its 1x DDR4 die. Additionally, SK Hynix 1x LPDDR4 technology uses a 0.191 Gb/mm2 bit density.


CONS OF DRAM             

  1.  short data-retention time (volatility)
  2. loss of data during readout (destructive read)
  3. Complex manufacturing process
  4. Data requires refreshing


  • DDRAM: Operates with higher transfer rates and better performance. It is also easily scalable replaceable. Thus, manufacturing process is easier.
  • UK III-V :the device can be written or erased without disturbing the data held in surrounding devices. Thus, no destructive read.
  • MRAM: MRAM can be used as a working memory that keeps its data EVEN when powered off, thus eliminating volatility. They are also non-destructive, and no refresh is needed.


  • Flash memory cells have a limited number of write and erase cycles before failing.
  • Currently costs a lot more per gigabyte than traditional hard drives forlarge storage capacities.
  • Most flash drives do not have have a write-protection mechanism
  • May require a special version of a program to run on a flash-based drive to protect from prematurely wearing out the drive.


  • VelocityFS by Tuxera writes data more efficiently to reduce wear associated with read/write cycles, thereby extending the lifetime of flash memory.
  • Having a write-protection hardware switch for keeping the contents of your drive safe from malware when you need to view them on a public computer.
  • RRAM offers small devices, much faster switching speed and at least a 10x improvement in wear life. The leader in this technology is Crossbar, with samples in the megabit range (compared to gigabits in flash die).
  • Flash suppliers  are responding to the challenge presented by these new technologies. Several device makers have created 3D devices that vertically stack storage cells over a single drive transistor. This approach increase yield and avoid extra capital investment to meet demand. One other benefit is a dramatic improvement in wear-out with the larger cell sizes.



From system startup to application launching, intel optane memory is smart technology that personalizes and accelerates computing experience on intel core-based pcs. It learns the most frequently used documents, images, videos, and applications; keeps them handy for quick access; and remembers them—even after powering off the PC. As computing habits change over time, intel optane memory adapts to continue to deliver a responsive, accelerated user experience.



Background power drain is a thing of the past with Intel Optane. Its memory redirects power and data to the most-used programs, so they run quickly, delivering remarkable responsiveness.


Uses a "least recently used" (LRU) approach to determine what gets stored in the fast cache.

Exploits 3D NAND fab techniques and various proprietary technologies to achieve super-low latency—as fast as 10 microseconds.

Optane DC Persistent Memory is pin-compatible with DDR4 and will be offered in packages of up to 512GB per stick.

 Originally released in 16GB and 32GB capacities, Intel later added a 64GB Optane Memory option.



  • MATERIALS USED: uses chalcogenide materials for both selector and storage parts of memory cell that are faster and more stable than traditional PCM materials
  • 3D XPoint has been stated to use electrical resistance and to be bit addressable. Switching is based on "bulk material properties”
  • Initially, a wafer fabrication facility in Lehi, Utah, operated by IM Flash Technologies LLC (an Intel-Micron joint venture) made small quantities of 128 Gbit chips in 2015. They stack two 64 Gbit planes. In early 2016 mass production of the chips was expected in 12 to 18 months.
  • Optane is based on Phase Change Memory (PCM), which an electrical current is used to change the state of a Chalcogenide glass material from crystalline to amorphous and back again.


  • 7th-generation Intel Core chip
  • Motherboard with an Intel chipset that supports Optane
  • At least one M.2 expansion slot
  • Any kind of RAM modules, storage drives, and graphics cards that will fit in a compatible motherboard


šCompatible only with Windows 10

šThe most dramatic improvements in performance come from a system with an older spinning hard drive, not increasingly-popular SSD storage.

šThe Optane system also increases power draw by a considerable margin.

šOptane’s caching system only works with the primary OS drive, and even then, only the primary partition.

A radically different technology: UK III-V


Simulations show that the device consumes very little power, with 100 times lower switching energy per unit area than DRAM, but with similar operating speeds.

The device can operate virtually disturb-free at 10-ns pulse durations, a similar speed to the volatile alternative, DRAM. This is derived from the triple-barrier RT mechanism used to transport the charge in and out of the device, which occurs at much lower voltages than other FG memories (i.e., Flash).


  • Using the interfacial misfit (IMF) array growth mode, III-V binary (InAs, AlSb, GaSb) and ternary (AlGaSb, AlGaAs) materials were grown on a lattice mismatched GaAs substrate by molecular beam epitaxy (MBE) under optimized growth conditions. Like Flash, the device is a floating-gate memory, with a junction-less channel to allow non-destructive read of the stored charge. However, there are no oxide layers. Instead, InAs/AlSb quantum wells and barriers provide profound electron confinement in the InAs floating gate.
  • The resemblance to Flash memory cells allows NAND or NOR Flash architectures to be directly implemented on the device to produce large arrays for write, erase, and read processes. This exclusive feature, combined with the increased predicts that the device can be implemented in large arrays as a low-power, nonvolatile, nondestructively read alternative to DRAM.


◦The memory cell, much like flash, uses a floating gate to store the memory state but, instead of using oxide isolation, the InAs floating gate is isolated by the anomalously large conduction band discontinuity with AlSb.

◦A compound-semiconductor charge-storage memory that exploits quantum phenomena for its operational advantages.


◦Where the new transistor departs from last years is that the new channel is normally-off (normally-on transistors cannot be paralleled in arrays) and has better-defined on and off states.

◦Nonvolatility is achieved due to the extraordinary band offsets of InAs and AlSb, providing a large energy barrier (2.1 eV), which prevents the escape of electrons.

◦A SPICE program (LTSpice) was used to combine the write/erase and read simulation results, which were produced using the software packages nextnano.MSB and nextnano++, respectively.



´Thus, we have discussed about the traditional memories, their drawbacks, and the technological changes that have evolved to overcome them.

´Scaling trends strive to bring down the critical dimension, while enhancing performance.

´We have seen the classic Intel’s Optane that works on Phase Change Memory, its performance and fabrication.

´We have also discussed about a radically different technology UK III-V that has reached only the simulation stage but promises a future of great expectations for the memory world.

´Memory is an ever-evolving field, with a wide range of applications at its disposal. Hopefully, the future for memory technology gives us the potential to achieve even greater deeds than ever before.