I am a graduate student pursuing maters in Electrical engineering a Arizona State University.
I have developed my interest towards digital design, VLSI design and RTL coding, basically in ASIC flow. I am currently looking for internship from Spring or summer 2020.
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Experience
I have worked on various projects in the ASIC flow. Concentrating on VLSI design, RTL codes, hardware blocks, python and more.
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Projects
Few of my projects are Custom layout of a 8 word x 8 bit single-port register file using ASU/ARM’s 7nm FinFET PDK, Design of NAND and RF bit standard cell using ASU/ARM’s 7nm FinFET PDK, Custom layout design of 4-bit Full adder using 32nm MOSFET PDK, Delay optimization and implementation of a logic path using 32nm MOSFET PDK, RTL design and implementation of FIR (finite impulse response) & LIFO (last in first out) using SystemVerilog, Created an optimized netlist of inverter chain and simulated it using python3.7, Detection of mines for submarine using Machine Learning.