I am a Computer Engineer with a Masters Degree in Electrical and Computer Engineering from the University of Florida. I am passionate about embedded systems and High-performance Computing.
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Experience
• Oracle JD Edwards EnterpriseOne® Technical Developer. Developed dynamic Reports and Applications using JD Edwards Enterprise One 9.1 toolset. Achieved a defect ratio of less than 2% in the deliverables
• Automated document output and delivery using Transform® software making document delivery easier and faster which resulted in a reduction of delivery time by 30%.
• Developed Python scripts to interface with Oracle Database and used SQL queries to retrieve information.
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Projects
1-D Time-Domain Convolution FPGA Accelerator using Smart Window Buffer (Sep 2018 – December 2018)
Tools: VHDL, C, Xilinx Vivado, ModelSim
• Implemented 1-D Time-Domain Convolution Accelerator on Zynq 7000 SoC’s Programmable logic. Used a smart Buffer to avoid redundant reads to the memory. Achieved a maximum Speedup of 16x when compared to the CPU implementation.
• Xilinx Vivado was used for Design, Analysis, and Implementation. The design included 3 major components: DRAM DMA Interface, Convolution Pipeline, and Smart Buffer.