Actively looking for challenging full-time opportunities in the area of Digital VLSI/ASIC design/ FPGA/ SoC/Verification (UVM)/ Validation.
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Experience
FPGA Design Engineer Intern, Colfax International (Santa Clara, CA) Aug 2019 – Dec 2019
• Resolved FPGA integration problems for link capture software, improved operations and provided exceptional client support.
• Maintained excellent attendance record, consistently arriving to work on time.
• Performed research into topics such as FPGA configuration using Linux Kernels in support of senior engineering staff needs.
• Utilized Python scripts to produce automatic FPGA flashing and updating Intel PACs to latest FIM/BMC firmware versions.
• Prepared detailed reports outlining Intel Arria 10GX/ Stratix 10GX FPGA for deploying open VINO tool kit.
• Conducted Validation and Testing (BIST) for the Intel PACs (Programmable Accelerator Cards) using Linux commands.
• Represented Colfax International at XILINX XDF 2019 event, a great team work experience.
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Projects
Functional Verification of AXI4 LITE to AHB bridge.
• Executed a Bus Functional Model using RTL design for the AXI4 LITE to AHB Bridge using System Verilog (Team of two).
• Implemented verification for protocol-based serial transaction from both ends of bridge using UVM methodology.
• Skills: System Verilog UVM library tools, VCD file analysis, GTK wave, Synopsys VCS.
Design of Bit movement block with AHB Bus arbiter.
• Performed Synthesis of bit movement block using DC Compiler for moving data to/from any bit location in memory.
• Built an RTL for 8-bit movement blocks with AHB bus using bandwidth arbitration method.
• Created AHB fabric, AHB bridge and AHB bus master connecting bit movement block (Team of three).
• Skills: System Verilog, Synopsys VCS NC Verilog simulation, Synopsys design compiler ultra, VCD file analysis, GTK wave.
Design and Synthesis of Spread Spectrum Correlator.
• Responsible for RTL design, synthesis, and debugging of a spread spectrum correlator using Verilog.
• Met timing requirements through STA.
• Built a unit running at 333Mhz, accepts sample every clock, and produces a correlation output (Team of two).
• Skills: System Verilog, Synopsys VCS NC Verilog simulation, Synopsys design compiler ultra, VCD file analysis, GTK wave.
Place and Route for chip-level implementation.
• Carried out a complete place and route post design synthesis using Cadence Virtuoso RTL-to-GDSII System 9.15 tool.
• Conducted Floor planning, Power Planning, Timing analysis as well as Clock Tree Synthesis (CTS) for the entire design.
• TSMC 0.18u ASIC library from OSU used for Standard Cell distribution.
• Accomplished gate level synthesis for following specifications Gates:16902, Clock period:25 units, Slack: +6.43 units.
Verification of I2C bus with APB interface using UVM.
• Formulated test bench using System Verilog and UVM and verified I2C bus controller with APB interface (Team of three).
• Skills: System Verilog UVM library tools, Synopsys VCS design compiler.
MIPS Instruction Set Architecture (ISA) design.
• Designed and simulated a subset of the MIPS Instruction Set Architecture (ISA) and executed dot product benchmark program
leveraging forward chaining technique in Verilog.
• Skills: Verilog, Synopsys VCS NC Verilog simulation, Synopsys RTL, VCD file analysis, GTK wave.
Traffic light control system and Vending Machine using FPGA.
• Constructed RTL for traffic light control system for multiple intersections supporting pedestrian signals on FPGA board.
• Built RTL for Vending Machine on FPGA board that accepts money, selects an item and gives out the change.
• Four 7-segment display employed for displaying product price and selection.
• Skills: Verilog, Altera Quartus-2 simulation/RTL/Synthesis, VCD file analysis, GTK wave, Altera’s Quartus cyclone-2 FPGA.