Master Student at San Jose state University .
Specialization in VLSI Digital Design and Verification
Looking for Co-op/Full time opportunity Graduating May 2021
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Experience
RTL design intern
RTL IP design on LVDSerdes io_buf, mlabs,ram, memory .
Functional coverage verification on the design block.
Developing Automation using Scripting Perl,Bash , TCL.
Synopsys VCS simulation and verification Test bench generate Random test cases. Debug the design using Verdi
Executing projects with different EDA tools (VCS, modelsim), repository tools (Perforce ) and debug tools (DVE, Verdi & Simvision)
Physical Design and Analog Design.
• Worked in Physical design Gen4 PCIe. Analog layout on DDR PHY and circuit design on sub-micro technology node's (14nm,10nm) on Intel specific Tool.
• Worked on design implementation of ESD methodology.
• EDA tools ICC1,ICC2, cadence design, design automation using scripting language TCl/TK, Perl, python.
• Good Knowledge of IR-drop analysis, Reliability Verification, SPEF parasitic Extraction.
• Part of Server processor group SDG and XPG at Intel.