I am a Graduate Student at the Maseeh College of Computer and Electrical Engineering in Portland State University. I am currently majoring in VLSI Physical Design and Computer Architecture. I am actively looking for Internship opportunities in the areas of RTL Design/Verification, Logic Design/Verification, Physical Design and other relevant domains.
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Projects
Modeled in system verilog the MIPS-lite ISA for in-order 5 stage pipeline.The design included data hazard detection and mitigation by stalling, flushing and forwarding methods.The project also included some metric quantification like number of instructions, breakdown of instruction frequencies, execution time with and without forwarding, speedup calculations etc,.
Studied the cause effect relationship for multiple parameters viz. max-cap, max-trans, max-fanout on two clocks (SDRAM clock and system clock). The effect studied included latency, skew, repeater counts, WNS and TNS for setup and hold.
Performed detailed routing of the design. The project included applying route guides, river routing, deriving pin access routing guides, DRS and LVS fixes, non-default routing for special nets, post-route optimization and ECO routing to address timing violations.
RTL Design and Synthesis for Synchronous Load Enable Register with Mux. Added Clock gating features including single and multi level clock gates. Performed balancing of the stages. Provided comparison of power and other QOR.
Designed L1 cache in System Verilog to study the impact of cache parameters (block size, associativity, replacement techniques etc.,) for different program traces.
In this project, an autonomous lamp post system was developed which will harness the solar energy from the nano-leaves which is used to illuminate the streets during night times, charge mobile batteries, and display carbon monoxide levels in the emission from the vehicles. Different sensors like LDR, IR, MQ7 air quality sensors etc have been deployed and Interfaced.