Master's in Science from San Jose State University, CA in Electrical Engineering and with specialization in the field of Digital IC/ASIC/FPGA Design and Verification.
· Programming Languages: Verilog, SystemVerilog, Universal Verification Methodology (UVM), Python, C.
· EDA Tools: Quartus Prime, Synopsys VCS, Synopsys design compiler, Mentor Graphics ModelSim, Xilinx ISE, Cadence Virtuoso, MATLAB, Proteus, Eagle.
· Other Skills: Digital Circuit Design,UVM, Static Timing Analysis, SoC Design, ASIC Design,
Computer Architecture, RTL Design, Assertions, Coverage, D Algorithm, Small Signal
Equivalent Circuits.
· Bus Protocol: AMBA 3 AHB-Lite, AMBA 3 APB Protocol.
· Operating System: Windows, Linux Mint
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Projects
1. AHB Fabric and Bridge Using Bandwidth Arbitrator[SoC Design, SystemVerilog]
Designed and implemented an AHB fabric for 10 masters and 11 slaves. Implemented a bridge for driving 8 Bit Move Blocks and LCD interface. A memory slave is included which provides the data for all masters and works as a default slave. Arbitration is done using a bandwidth arbitrator which decides the master to be granted based on each bandwidth assigned to master. BW arbitrator consists an internal round robin and priority arbitrator.
2. Bit Move Block [SoC Design, SystemVerilog] Fall 2019
Block has two interfaces. One to read and write registers, another for the block to read and write memory, and a third interface for some status and completion information.The data is accessed at a bit level. This is a performance based block which takes 10 cycles for get going and finishing after which data is moved to or from memory. Working on placing this block as a master and slave on AHB Bus.
3. A Simple Spread Spectrum Correlator [ASIC Design, Verilog] Spring 2019
Designed and implemented a simple spread spectrum correlator which is used to recover a signal that has been spread with a Gold Code using phase shift keying. Project is a unit that runs at 333Mhz, can accept a base band sample every clock, and produces a correlation output.
4. 16 Bit Half Precision Floating Point Adder Using Verilog [Computer Architecture] Spring 2019
Designed and implemented a 16-bit half precision floating point adder which is based on IEEE 754 standard.Verilog HDL is used for implementing the adder and simulated using GTK wave.
5. Traffic Signal System using Verilog Fall 2018
Designed and implemented an automated traffic signal system for two intersections and two pedestrian crossings. The system was implemented using FPGA board. The coding was done using Verilog and synthesis was done using Quartus Prime Software.
6. Vending Machine [FPGA, Verilog] Fall 2018
Designed a Vending Machine that can dispense any of the three different products of three different prices.Based on the input amount and selection, particular product can be dispensed. The system was implemented using FPGA board. The coding was done using Verilog and synthesis was done using Quartus Prime Software.