I had completed A.M.I.E.T.E (Equivalent to B.E/B.Tech) in ECE by Dec 2002. I pursued M.Tech with VLSI DESIGN as specialization in S.R.M University by Jun 2005.
Experience
From Aug 2005 to May 2019 worked as Associate Professor in ECE Department in Various Colleges/Universities across INDIA.
Projects
As I want to shift to companies side I took Training in Design Verification (VLSI Domain) at Qsocs Bangalore from July 2019 to March 2020.
Projects I had completed are on FIFO, APB, AHB Protocols verification using SystemVerilog/verilog Languages.