Master's in Science from San Jose State University, CA in Electrical Engineering and with specialization in the field of Digital IC/ASIC/FPGA Design and Verification.
· Programming Languages: Verilog, SystemVerilog, Universal Verification Methodology (UVM), Python, C.
· EDA Tools: Quartus Prime, Synopsys VCS, Synopsys design compiler, Mentor Graphics ModelSim, Xilinx ISE, Cadence Virtuoso, MATLAB, Proteus, Eagle.
· Other Skills: Digital Circuit Design,UVM, Static Timing Analysis, SoC Design, ASIC Design,
Computer Architecture, RTL Design, Assertions, Coverage, D Algorithm, Small Signal
Equivalent Circuits.
· Bus Protocol: AMBA 3 AHB-Lite, AMBA 3 APB Protocol.
· Operating System: Windows, Linux Mint